Fabrication of polycrystalline semiconductor infrared detector

ABSTRACT

Methods of fabrication and monolithic integration of a polycrystalline infrared detector structure deposit Group III-V compound semiconductor materials at a low deposition temperature within a range of about 300° C. to about 400° C. directly on an amorphous template. The methods provide wafer-level fabrication of polycrystalline infrared detectors and monolithic integration with a readout integrated circuit wafer for focal plane arrays.

CROSS-REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENTBACKGROUND 1. Technical Field

The invention relates to infrared (IR) detectors fabricated usingpolycrystalline semiconductor materials. In particular, the inventionrelates to a polycrystalline IR detector and a fabrication technique onamorphous templates.

2. Description of Related Art

Infrared (IR) detectors are key components of focal plane arrays used insensing and imaging applications in short-wave infrared (SWIR),medium-wave infrared (MWIR), and long-wave infrared (LWIR) spectralbands. The materials and processes used to fabricate IR detector impactperformance metrics such as dark current density and spectral response,for example. IR detectors typically are fabricated usingsingle-crystalline semiconductor materials to provide a level ofsensitivity and performance in sensing and imaging applications in theabove-mentioned spectral bands, for example for military applications.However, concomitant with performance and sensitivity is cost tomanufacture the single-crystalline IR detectors and focal plane arraysfor the specific applications. In particular, the manufacture ofsingle-crystalline IR detectors and the focal plane arrays in which theyare assembled is time-consuming and costly. Therefore, the performancemetrics of the IR detectors in a particular application and the cost ofthe IR detectors present possible necessary trade-offs.

Photon detectors used in photovoltaic applications have been fabricatedand evaluated using polycrystalline semiconductor materials, inparticular for the manufacture of low cost solar cells. However,polycrystalline semiconductor materials characteristically have crystaldefects, such as vacancies, dislocations and grain boundaries. Thesecrystal defects typically result in detector performance degradation,for example due to excess dark current, which can limit the usefulnessof polycrystalline semiconductor materials in sensitive SWIR, MWIR andLWIR applications. While progress with polycrystalline photon detectorsfor photovoltaic applications has been made to bring down cost whileoffering acceptable or tolerable performance in solar cell applications,an IR detector for sensitive SWIR, MWIR and LWIR applications using alower cost fabrication technique and materials is still needed.

BRIEF SUMMARY

In some embodiments of the present invention, a method of fabricating apolycrystalline infrared (IR) detector is provided. The method offabricating comprises providing an amorphous template. The method offabricating further comprises depositing a Group III-V compoundsemiconductor material directly on the amorphous template at a lowdeposition temperature that is within a range of about 300° C. to about400° C. The deposition comprises doping the Group III-V compoundsemiconductor material with a dopant profile to form the polycrystallineIR detector structure having a detector semiconductor junction.

In other embodiments of the present invention, a method of monolithicintegration of an infrared (IR) detector in a focal plane array isprovided. The method of monolithic integration comprises providing areadout integrated circuit (ROIC) wafer with an amorphous surface. Themethod of monolithic integration further comprises depositing GroupIII-V compound semiconductor materials directly on the amorphous surfaceof the ROIC wafer at a low temperature within a range of about 300° C.to less than 400° C. to form a polycrystalline IR detector structurehaving a semiconductor junction. The polycrystalline IR detectorstructure directly on the ROIC wafer forms a monolithically integratedstructure to provide pixels of an IR focal plane array.

In some embodiments of the present invention, a polycrystalline mid-waveinfrared (MWIR) detector structure is provided. The polycrystalline MWIRdetector structure comprises an amorphous template, and apolycrystalline Group III-V compound semiconductor directly on theamorphous template. The polycrystalline MWIR detector structure furthercomprises a semiconductor junction in the polycrystalline Group III-Vcompound semiconductor, and electrically conductive contacts at oppositeends of the semiconductor junction. The polycrystalline MWIR detectorstructure has one or both of a dark current characteristic and a dioderesponse substantially comparable to a single-crystalline Group III-Vcompound semiconductor MWIR detector.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features of embodiments in accordance with the principlesdescribed herein may be more readily understood with reference to thefollowing detailed description taken in conjunction with theaccompanying drawings, where like reference numerals designate likestructural elements, and in which:

FIG. 1 illustrates a flow chart of a method of fabricating apolycrystalline infrared (IR) detector in an example, according to anembodiment consistent with the principles of the present invention.

FIG. 2 illustrates a side view of a polycrystalline IR detectorfabricated according to the method of FIG. 1 in an example, according toan embodiment consistent with the principles of the present invention.

FIG. 3 illustrates a flow chart of a method of monolithic integration ofan infrared (IR) detector in a focal plane array in an example,according to an embodiment consistent with the principles of the presentinvention.

FIG. 4 illustrates a graph of an X-ray diffraction spectrum of afabricated polycrystalline InAs barrier detector structure in anexample, according to an embodiment consistent with the principles ofthe present invention.

FIG. 5A illustrates a graph of a dark current density characteristic ofthe fabricated polycrystalline InAs barrier detector structure in anexample, according to an embodiment consistent with the principles ofthe present invention.

FIG. 5B illustrates a graph of a spectral response of the fabricatedpolycrystalline InAs barrier detector structure in an example, accordingto an embodiment consistent with the principles of the presentinvention.

FIG. 6 illustrates a graph of a dark current density characteristic of asingle-crystalline IR device as a comparison to the dark current densitycharacteristic results illustrated in the FIG. 5A graph for thefabricated polycrystalline InAs barrier detector structure in anexample, according to an embodiment consistent with the principles ofthe present invention.

Certain examples and embodiments have other features that are one of inaddition to and in lieu of the features illustrated in theabove-referenced figures. These and other features are detailed belowwith reference to the above-referenced figures.

DETAILED DESCRIPTION

Embodiments of the present invention are directed to providing sensitiveIR detectors and systems that incorporate the IR detectors at lower costthan using traditional manufacturing. For example, traditional focalplane array manufacturing is a die-level process that relies upon dicingboth a silicon readout integrated circuit (ROIC) wafer (e.g., typically200 mm in diameter) and a compound semiconductor detector array wafer(e.g., typically 75-150 mm in diameter) into rectangular die (e.g.,typical edge length of 10-40 mm). Individual ROIC die and individualcompound semiconductor detector die are then interconnected using anarray of indium bumps, achieved by compression bonding together of therespective individual die. The die-level process for focal plane arraymanufacture remains the norm.

On the other hand, wafer-level fabrication of IR detectors for focalplane arrays can reduce cost by eliminating time-consuming manufacturingsteps, traditionally performed at die-level rather than at fullwafer-level. However, wafer-level fabrication has been fraught withpotential problems affecting device performance. For example, inherentin wafer-level fabrication of IR detectors for assembly in focal planearrays is that the surface of the ROIC wafer is substantially amorphousor non-crystalline. Deposition of semiconductor material directly on anamorphous surface (or even a polycrystalline surface) has potentialundesirable consequences. For example, typical deposition or growthtechniques for semiconductor materials directly on such surfaces resultin semiconductor structures that are polycrystalline, notsingle-crystalline, and therefore, have crystal defects that potentiallycan impact performance. Therefore, without a solution, the problemsassociated with crystal defects in polycrystalline semiconductormaterials and the impact that crystal defects may have on deviceperformance metrics have hindered progress with wafer-level fabrication.

Embodiments of the present invention address these difficulties andprovide a solution for fabrication of IR detector on amorphous surfaces,including wafer-level fabrication, e.g., directly on the surface of ROICwafers. In particular, embodiments consistent with the principles of thepresent invention provide an IR detector and a fabrication method thatboth include polycrystalline semiconductor detector structures and usesconventional deposition equipment to deposit or grow, at a lowtemperature, polycrystalline semiconductor materials directly onamorphous templates to form the polycrystalline semiconductor detectorstructures (i.e., ‘direct fabrication’). Moreover, the methods inaccordance with the embodiments herein provide a polycrystalline IRdetector having a performance metric that may be comparable to acounterpart performance metric of a similar single-crystalline IRdetector.

The amorphous template may be a wafer having an amorphous ornon-crystalline surface, e.g., a ROIC wafer. In accordance with someembodiments herein, IR detector fabrication uses wafer-level processingand low-temperature deposition techniques to monolithically integratethe IR detector directly on a ROIC wafer for focal plane arraymanufacture. In some embodiments, the present invention enables theintegration of a detector array and a silicon ROIC wafer to be achievedin a single process at full wafer-level, without interconnection throughindium bumps. As such, substantial manufacturing cost-savings relativeto the conventional manufacturing of focal plane arrays may be realized.

Moreover, in accordance with some embodiments herein, the directfabrication process at low temperature produces a unique polycrystallinesemiconductor IR detector structure that has performance metricssubstantially comparable to those of a conventional single-crystallineIR detector of the same semiconductor materials. In particular, thepolycrystalline IR detector on an amorphous template in accordance withthe present invention has exhibited comparable performance metrics, suchas dark current density and diode spectral response. As such, in someembodiments herein, a polycrystalline IR detector fabricated directly onthe amorphous surface of a ROIC wafer and the focal plane arrays thatincorporate them, in accordance with the principle described herein, mayavoid costly die-level assembly of individual detector chips to ROICchips for focal plane array manufacture without sacrificing performance,for example.

As used herein, the article ‘a’ is intended to have its ordinary meaningin the patent arts, namely ‘one or more’. For example, ‘a material’means one or more materials and as such, ‘the material’ means ‘thematerial(s)’ herein. Also, any reference herein to ‘top’, ‘bottom’,‘upper’, ‘lower’, ‘up’, ‘down’, ‘front’, back’, ‘left’ or ‘right’ withrespect to direction, or ‘first’ or ‘second’ with respect to priority,order or sequence, for example, is not intended to be a limitationherein. Herein, the term ‘about’ when applied to a value generally meanswithin the tolerance range of the equipment used to produce the value,or may mean plus or minus 20%, or plus or minus 10%, or plus or minus5%, or plus or minus 1%, unless otherwise expressly specified. Further,the term ‘substantially’ as used herein means a majority, or almost all,or all, or an amount within a range of about 51% to about 100%.Moreover, examples and embodiments herein are intended to beillustrative only and are presented for discussion purposes and not byway of limitation.

According to some embodiments of the present invention, a method offabricating a polycrystalline infrared (IR) detector structure isprovided. FIG. 1 illustrates a flow chart of a method 100 of fabricatinga polycrystalline infrared (IR) detector structure in an example,according to an embodiment consistent with the principles of the presentinvention.

The method 100 of fabricating polycrystalline infrared (IR) detectorstructure comprises providing 110 an amorphous template. Amorphoustemplates are described further below, and include, but are not limitedto, a semiconductor wafer, e.g., a wafer comprising embedded orunderlying microelectronic circuitry. The method 100 of fabricatingpolycrystalline infrared (IR) detector structure further comprisesdepositing 120 a Group III-V compound semiconductor material directly onthe amorphous template at a low deposition temperature that is within arange of about 300° C. to about 400° C. The deposition 120 comprisesdoping the Group III-V compound semiconductor material with a dopantprofile to form a polycrystalline IR detector structure having adetector semiconductor junction. Doping of the Group III-V compoundsemiconductor material is performed simultaneously with the depositionof the Group III-V compound semiconductor material, or in someembodiments, a portion of the doping may be performed after the GroupIII-V compound semiconductor material is deposited, for example usingion implantation of dopant materials.

The deposition 120 of a Group III-V compound semiconductor material, inaccordance with the method 100 of fabrication, uses a deposition orgrowth technique including, but not limited to, one or more of molecularbeam epitaxy (MBE) and a chemical vapor deposition (CVD) technique, suchas metal organic CVD (MOCVD), for example. Both MBE and MOCVD arecompatible with the low deposition temperature that is within the rangeof about 300° C. to about 400° C. Moreover, the deposition techniquesare compatible with either simultaneously doping or subsequently dopingthe semiconductor materials, in accordance with the method 100 offabrication. For example, simultaneously doping includes, for example,providing a flux of dopant atoms with the constituent Group III-Vcompound semiconductor material during deposition 120.

By ‘low temperature’ of deposition, it is meant a deposition temperaturebelow a critical temperature of the amorphous template. By ‘criticaltemperature’ it is meant a temperature at which continued exposure atthe critical temperature will degrade microelectronic circuitryunderlying the amorphous template. By ‘continued exposure’ it is meantat least a deposition time period of depositing 120 the Group III-Vcompound semiconductor material that form the polycrystalline IRdetector structure. In some embodiments, the critical temperature isbelow 450° C., or may be less than about 400° C., e.g., forsilicon-based amorphous templates. In some embodiments, the range of thelow deposition temperature used herein is within about 300° C. to about375° C., or within about 300° C. to about 350° C., or within about 300°C. to about 325° C. In an embodiment, the low deposition temperatureused is about 325° C.

In some embodiments, the amorphous template provided 110 in accordancewith the method 100 includes, but is not limited to, a ceramicsubstrate, a glass substrate, a metal substrate, a semiconductorsubstrate or wafer, or a semiconductor substrate or wafer with amorphoussurface. By ‘amorphous surface’ it is meant that the substrate or waferis amorphous or non-crystalline (e.g., an amorphous semiconductorwafer), or the substrate or wafer has an amorphous surface that is oneor both (a) by virtue of the wafer being amorphous and (b) due to anamorphous layer (e.g., an oxide layer) being on the substrate or wafersurface. In an example, the amorphous template is a silicon substratehaving a silicon dioxide layer on the surface of the silicon substrate,for example, an oxidized Czochralski silicon substrate.

In some embodiments, the amorphous template is an amorphous surface of areadout integrated circuit (ROIC) wafer used in the manufacture of focalplane arrays. The ROIC wafer is a semiconductor wafer made fromsemiconductor materials that facilitate and support integrated circuitformation, such as silicon, germanium or a compound semiconductormaterial, for example gallium arsenide (GaAs). The ROIC wafer may be asingle-crystalline semiconductor wafer (e.g., silicon-based wafer) thatcomprises fabricated integrated circuitry (e.g., the above-mentioned‘underlying microelectronic circuitry’) for the operation of a focalplane array. For example, an ROIC wafer may typically include an arrayof preamplifiers and switches. The fabrication of the integratedcircuitry on or in the readout wafer renders the surface of the ROICwafer as amorphous. Moreover, the ROIC wafer surface may include anamorphous layer of an interlayer dielectric material (ILD). ILDsfacilitate isolation of electrical contacts at the wafer surface thatconnect to various underlying microelectronic circuitry.

In accordance with the method 100 of fabrication, the provided 110amorphous template may include the above-described ROIC wafer. Thecritical temperature of a ROIC wafer is about 450° C., at least due tothe fabricated integrated circuitry on the ROIC wafer. The deposition120 of the IR detector semiconductor materials, according to the method100, uses a temperature below the critical temperature of the ROICwafer, as well as below other amorphous templates, in accordance withthe principles described herein.

Moreover, in the embodiments where the provided 110 amorphous templateis an ROIC wafer, the Group III-V compound semiconductor material isdeposited 120 directly on the amorphous surface of the ROIC wafer anddoped to form the polycrystalline IR detector structure. For example,the temperature range of depositing 120 the Group III-V compoundsemiconductor may be about 300° C. to about 350° C. As such, the method100 of fabrication monolithically integrates the polycrystalline IRdetector structure with the ROIC wafer circuitry to simultaneously forma plurality of focal plane arrays (FPA) that can be separated bysubsequent dicing into individual FPA die.

In these embodiments, the monolithic integration eliminates cumbersomeconventional die-level additional hybridization steps where the IRdetectors are fabricated separately, sub-divided into individual chipsor die that are then manually assembled and electrically connected tosub-divided die of the ROIC wafer, e.g., using one or more ofconventional indium bumping and wire bonding, as described above.Moreover, the polycrystalline IR detector structure fabricated using themethod 100 may have one or both of a dark current characteristic and adiode response substantially comparable to single-crystalline GroupIII-V compound semiconductor IR detectors, in some embodiments.

The Group III-V compound semiconductor material that is deposited 120comprises one or more elements from Group III alloyed with one or moreelements from Group V of the Periodic Table of the Elements. Examples ofthe Group III-V compound semiconductor material include one or more ofindium (In), aluminum (Al) and gallium (Ga) from Group III with one ormore of phosphorous (P), arsenic (As) and antimony (Sb) from Group V. Insome embodiments, the Group III-V compound semiconductor materialincludes one or more of In, Al, As and Sb, or two or more of In, Al, Asand Sb. In some embodiments, the Group III-V compound semiconductormaterial includes one or more deposition layers of InAs, AlSb, AlGaSb,InSb, and InAsSb. In some embodiments, the polycrystalline IR detectorstructure fabricated according to the method 100 of fabrication may be aMWIR detector, for example an InAsSb MWIR detector or an InAs MWIRdetector.

As provided above, the method 100 of fabrication further comprisesdepositing 120 the Group III-V compound semiconductor material with adopant profile to form the polycrystalline IR detector structure havinga detector semiconductor junction. The detector semiconductor junctionmay be a p-n type junction, for example. FIG. 2 illustrates a side viewof a polycrystalline IR detector 200 fabricated according to the method100 of FIG. 1 in an example, according to an embodiment consistent withthe principles of the present invention.

Referring to the polycrystalline IR detector 200 illustrated in FIG. 2,in some embodiments of the method 100 of fabrication of FIG. 1, a firstcontact layer 203 of a first Group III-V compound semiconductingmaterial is deposited 120 directly on the provided 110 amorphoustemplate 201. The first contact layer 203 is polycrystalline andincludes a first doping level 223 of the dopant profile. In someembodiments, the first contact layer 203 is doped to provide an n⁺-typeor p⁺-type dopant and doping level 223 adjacent to the amorphous surfaceof the provided 110 template 201 to render the first contact layersubstantially electrically conductive. Further, in some embodiments, thefirst contact layer 203 is doped to include a doping level gradientwithin the first contact layer 203 that transitions from substantiallyelectrically conductive to relatively less electrical conductivity. Inparticular, the transition is from the corresponding n⁺ or p⁺ dopinglevel 223 to a corresponding n⁻ or p⁻ doping level 223 a at a surface ofthe deposited first contact layer 203 (i.e., doping level 223 is greaterthan doping level 223 a).

In some embodiments, the n or p doping level may be within a range ofabout 10¹⁵ cm⁻³ to about 10¹⁶ cm⁻³, and the n⁺ or p⁺ doping level may bewithin a range of about 10¹⁷ cm⁻³ to about 10¹⁹ cm⁻³, for example.Moreover, the doping level for the n⁻ or p⁻ doping level may be within arange of about 10¹³ cm⁻³ to about 10¹⁴ cm⁻³, for example.

Referring again to FIG. 2, the polycrystalline IR detector 200 furtherincludes an absorber layer 205 of a second Group III-V compoundsemiconducting material that is deposited 120 on the first contact layer203. The absorber layer 205 is also polycrystalline and includes asecond doping level 225 of the dopant profile. The absorber layer 205 isdoped to provide the corresponding n⁻-type or p⁻-type dopant and thesecond doping level 225. In some embodiments, the second doping level225 may be substantially similar to the adjacent surface doping level223 a of the first contact layer 203.

Further with respect to FIG. 2, the polycrystalline IR detector 200 insome embodiments, further includes a barrier layer 207 of a third GroupIII-V compound semiconducting material that is deposited 120 on theabsorber layer 205. The barrier layer 207 is also polycrystalline andincludes a third doping level 227 of the dopant profile. The barrierlayer 207 is doped to provide either the same or an opposite dopant typeto the n⁻-type or p⁻-type dopant of the absorber layer 205. Moreover, insome embodiments, the third doping level 227 of the barrier layer 207 isgreater than the second doping level 225 of the absorber layer 205.

The polycrystalline IR detector 200 illustrated in FIG. 2 furtherincludes a second contact layer 209 of a fourth Group III-V compoundsemiconducting material that is deposited 120 on the barrier layer 207.The second contact layer 209 is polycrystalline and includes a fourthdoping level 229 of the dopant profile. The second contact layer 209 isdoped to provide either a corresponding or an opposite dopant type ofthe absorber layer 205, but has an increased doping level 229 of n⁺-typeor p⁺-type dopant relative to the doping level 225 of the absorber layer205. Moreover, the higher fourth doping level 229 renders the secondcontact layer 209 relatively more electrically conductive than theabsorber layer 205. However, the fourth doping level 229 of the secondcontact layer 209 may be substantially similar to the first doping level223 of the first contact layer 203, in some embodiments.

In some embodiments, the above-described first, second, third and fourth(i.e., ‘first through fourth’) doping levels 223, 223 a, 225, 227, 229and dopant types of the various first through fourth Group III-Vcompound semiconducting material layers form the dopant profile of thedetector semiconductor junction of the polycrystalline IR detector 200fabricated in accordance with the method 100 of fabrication. Dopantmaterials used for the method 100 of fabricating include, but are notlimited to, beryllium (Be), silicon (Si), carbon (C), and tellurium(Te).

In some embodiments, the first dopant level 223 of the first contactlayer 203 and the fourth doping level 229 of the second contact layer209 each is within the range of about 1×10¹⁷ cm⁻³ to about 9×10¹⁷ cm⁻³.Moreover, the first doping level 223 may decrease to within a range ofabout 5×10¹⁵ cm⁻³ to about 5×10¹⁶ cm⁻³ to the surface doping level 223 aat the surface of the first contact layer 203. In some embodiments, theabsorber layer 205 second doping level 225 is within the range of about1×10¹⁵ cm⁻³ to about 5×10¹⁶ cm⁻³, and for example, may be thesubstantially the same as the level of the adjacent surface doping level223 a of the contact layer 203. The barrier layer 207 third doping level227 is within the range of about 1×10¹⁵ cm⁻³ to about 1×10¹⁷ cm⁻³, insome embodiments.

In some embodiments, the first, second, third and fourth Group III-Vcompound semiconducting materials deposited 120 to fabricate thepolycrystalline IR detector 200 may one or both of be stoichiometricallydifferent and comprise different semiconducting materials. In otherembodiments, one or more of the first, second, third and fourth GroupIII-V compound semiconducting materials may comprise the substantiallythe same materials (albeit, with possible stoichiometric differences),while others of the first, second, third and fourth Group III-V compoundsemiconducting materials may comprise different materials.

For example, the first Group III-V compound semiconducting material(i.e., contact layer 203) may comprise substantially the samesemiconducting materials as the second Group III-V compoundsemiconducting material (i.e., absorber layer 205). Moreover, in someexamples, the second Group III-V compound semiconducting material (i.e.,absorber layer 205) may comprise a different semiconducting materialthan the third Group III-V compound semiconducting material (i.e.,barrier layer 207). In some examples, the first and fourth Group III-Vcompound semiconducting materials (i.e., first and second contact layers203, 209) may comprise substantially the same semiconductor materials.Other variations in the similarities and differences between thecompositions of the first through fourth Group III-V compoundsemiconducting materials are also within the scope of the principlesdescribed herein and those described above are not intended as alimitation.

In an embodiment of the polycrystalline IR detector 200 fabricated usingthe method 100, the Group III-V compound semiconducting materials of thefirst contact layer 203, the absorber layer 205 and the second contactlayer 209 each comprises InAsSb. Further in this embodiment, the barrierlayer 207 comprises AlSb to form a polycrystalline InAsSb MWIR detector200. In another embodiment, the barrier layer 207 comprises AlGaAsSb toform another polycrystalline MWIR detector 200.

In some embodiments of the fabricated polycrystalline IR detector 200according to the method 100, the thickness of the first contact layer203 may be within a range of about 750 angstroms (Å) to about 2,000 Å,wherein a thickness region of the gradient or transition to the surfacedoping level 223 a of the first contact layer 203 is about one-third toabout three-fourths of the first contact layer thickness. Moreover insome embodiments, the thickness of the absorber layer 205 may be withina range of about 3,500 Å to about 35,000 Å. The thickness of the barrierlayer 207 may be within a range of about 1000 Å to about 2000 Å, in someembodiments. Further, in some embodiments, the thickness of the secondcontact layer 209 may be within a range of about 500 Å to about 1,500 Å.

Other ranges of various layer thicknesses are also within the scope ofthe principles described herein and those described above are notintended as a limitation. For example, the thickness of the absorberlayer 205 may be within a range of about one micron to about fivemicrons; or about one micron to about two microns, or about two micronsto about four microns, or two microns to about three microns, or threemicrons to about five microns. In another example, the thickness of thebarrier layer 207 may be within a range of about 100 nm to about 400 nm;or about 200 nm to about 400 nm; or about 100 nm to about 200 nm.Moreover, the thickness of the second contact layer 209 may besubstantially similar to the thickness of the first contact layer 203 insome examples.

In some embodiments, the method 100 of fabricating a polycrystalline IRdetector structure may further comprise passivating grain boundaries ofthe polycrystalline IR detector in a controlled manner with hydrogenatoms. The grain boundaries may be passivated in a controlled manner inaccordance with any of the methods described in a co-pending U.S. patentapplication Ser. No. 15/885,693, entitled “Grain Boundary Passivation ofPolycrystalline Materials,” which is filed the same day as the presentapplication, and has the same Assignee. This co-pending application isincorporated by reference in its entirety herein.

For example, in some embodiments, the controlled grain boundarypassivation comprises exposing the polycrystalline IR detector (e.g.,polycrystalline IR detector 200) to controlled pulses of a plasma at atemperature maintained within a range of about 100° C. to less than 200°C. for a period of time. The plasma comprises a mixture of a carrier gasand hydrogen gas, wherein the hydrogen gas is mixed into a plasma of thecarrier gas. The carrier gas plasma breaks some of the hydrogen gas intoelemental hydrogen (i.e., hydrogen atoms) in the plasma and the hydrogenatoms are carried to the polycrystalline semiconductor structure by thecarrier gas for incorporation into the grain boundaries. The hydrogenand carrier gases may be mixed in a ratio of gases that may be within arange of about 0.1:10 to about 1.0:10 hydrogen to carrier gas.

Moreover, in some embodiments, the controlled pulses may comprise aplasma pulse duration within a range of about 5 seconds to about 20seconds, and a rest time between the plasma pulses within a range ofabout 2 seconds to about 10 seconds. An exposure period of time ofpulsing may be within a range of about 15 minutes to about 240 minutes.Moreover, a pulse power may be within a range of about 20 Watts to about300 Watts. It is within the scope of the present application herein thatany of the ranges described in the above-mentioned co-pending U.S.application may be used.

Characteristics of the plasma pulse may comprise one or more of aquantity of the pulses, a pulse duration, a rest period between thepulses, and a pulse power, for example, during the time period of thepulsed exposure. A combination of gas flows of the hydrogen gas and thecarrier gas in the formed plasma gas mixture may further facilitateincorporation of the hydrogen atoms into the grain boundaries. Forexample, the gas flow of the hydrogen gas may be a fraction of the gasflows of the carrier gas and the carrier gas plasma. In an embodiment,the gas flow of the carrier gas may be about thirty times, and the gasflow of the carrier gas plasma may be about eighty times, more than thegas flow of the hydrogen gas in the formed plasma gas mixture, forexample.

In some embodiments, the controlled grain boundary passivation of thepolycrystalline IR detector may further alleviate an impact of grainboundary defects in the polycrystalline semiconductor material and mayfurther improve performance metrics of the polycrystalline IR detectorstructure fabricated using the method 100. For example, the hydrogenatoms may combine with various semiconductor atoms (e.g., In, As, Sb,etc.) in the polycrystalline structure that may have dangling bonds,such as those bonds found in grain boundaries or on surfaces. A hydrogenatom may combine with a dangling bond so that the dangling bond does nottrap a photo carrier electron, for example. In some embodiments, thepolycrystalline IR detector 200 further comprises hydrogen atomsembedded in polycrystalline grain boundaries of the polycrystallineGroup III-V compound semiconductor as a passivation.

According to some embodiments of the present invention, a method ofmonolithic integration of an IR detector in a focal plane array isprovided. FIG. 3 illustrates a flow chart of a method 300 of monolithicintegration of an IR detector in a focal plane array in an exampleaccording to the principles described herein.

The method 300 of monolithic integration comprises providing 302 areadout integrated circuit (ROIC) wafer having an amorphous surface. Themethod 300 of monolithic integration further comprises depositing 304Group III-V compound semiconductor materials directly on the amorphoussurface of the ROIC wafer at a low temperature within a range of about300° C. to less than 400° C. The deposition 304 comprises forming asemiconductor junction in the Group III-V compound semiconductormaterials to form a polycrystalline IR detector structure that ismonolithically integrated with the ROIC wafer. The ‘integralpolycrystalline IR detector-ROIC monolithic structure’ formed by themethod 300 provides pixels of a focal plane array (FPA).

In some embodiments of the method 300 of monolithic integration, thetemperature range of the deposition 304 is substantially similar to thetemperature ranges set forth above for the method 100 of fabricating apolycrystalline IR detector structure. For example, the temperaturerange may be within about 300° C. to about 375° C. Moreover, thedeposition 304 may use a deposition technique including but not limitedto, MBE or MOCVD, for example. In some embodiments, the Group III-Vcompound semiconductor materials deposited 304 in accordance with themethod 300 of monolithic integration are substantially similar to theGroup III-V materials described above for the method 100 of fabricatinga polycrystalline IR detector structure. For example, the compoundsemiconductor materials of the IR detector may comprise two or more ofindium, aluminum, gallium, arsenic and antimony.

Further, according to the method 300 of monolithic integration, thesemiconductor junction is provided by doping the Group III-V materials.In some embodiments, the semiconductor junction is provided usingsubstantially similar dopants, dopant levels, and dopants profilesdescribed above for the detector semiconductor junction of thepolycrystalline IR detector structure formed in the method 100 offabrication (e.g., the detector 200 of FIG. 2). For example, thesemiconductor junction may be a p-n type junction, or may be an n-p typejunction. In some embodiments, doping to provide a semiconductorjunction with a dopant profile in both the method 100 of fabricating andthe method of 300 monolithic integration may be performed with thedeposition of the Group III-V semiconductor materials or a portion ofthe doping may be provided thereafter.

In some embodiments, the polycrystalline IR detector structure formed inaccordance with the method 300 of monolithic integration may besubstantially similar to the polycrystalline IR detector structurefabricated by the method 100 of fabrication. For example, thepolycrystalline IR detector structure portion of the ‘integralpolycrystalline IR detector-ROIC monolithic structure’ may comprise anabsorber layer and a barrier layer sandwiched between first and secondcontact layers, as described above with respect to polycrystalline IRdetector 200 of FIG. 2 and with respect to the method 100 of fabricationof FIG. 1. Moreover, the ROIC wafer used in the method 300 of monolithicintegration may be substantially the same as the ROIC wafer describedabove as an example of the amorphous template used in the method 100 offabrication. For example, the ROIC wafer may be a silicon-based ROICwafer having underlying microelectronic circuitry comprising a pluralityof amplifiers and switches.

In particular, in accordance with the method 300 of monolithicintegration, the ROIC wafer comprises a plurality of amplifiers andswitches with circuit contacts at the ROIC wafer surface. The monolithicintegration of the method 300 herein not only directly physicallyconnects the ROIC wafer and the polycrystalline IR detector structuretogether but also forms intrinsic electrical connections between variouscircuit contacts of the ROIC wafer and the polycrystalline IR detectorstructure. For example, the monolithic integration includes multipledepositions 304 of respective Group III-V materials with masking andetching between depositions to define pixels isolated from one another,but which have contact to unit-cell contact metallization in the ROICwafer. Moreover, inter-layer dielectric (ILD) materials patterned withelectrical interconnects provide an interface between the ROIC wafersurface and the deposited 304 first contact layer of the Group III-Vcompound semiconductor materials. In some embodiments, the resulting‘integral polycrystalline IR detector-ROIC monolithic structure’provides a pixel or an array of pixels of an IR FPA.

Moreover, the method 300 of monolithic integration as described hereinavoids conventional time-consuming manufacturing or assembly steps thatinclude dicing an IR detector wafer and the ROIC wafer into respectiveindividual die and manually indium bumping or wire bonding theindividual IR detector die to the ROIC wafer die to assembly pixels ofan IR FPA, as in conventional FPA manufacturing. In some embodiments,the ‘integral polycrystalline IR detector-ROIC monolithic structure’ inaccordance with the method 300 may be a MWIR FPA.

In some embodiments, the method 300 of monolithic integration mayfurther comprise passivating grain boundaries of the polycrystalline IRdetector-ROIC monolithic structure in a controlled manner with hydrogenatoms. The grain boundary passivation may be substantially similar tothe passivation described above for the method 100 of fabrication, andincludes the above-referenced co-pending application, incorporated byreference in its entirety. The grain boundary passivation with hydrogenatoms in a controlled manner using gas plasma pulses at low temperature,i.e., less than about 200° C., as described in the above-incorporated byreference co-pending application, may further improve performancemetrics of the polycrystalline IR detector portion of thepolycrystalline IR detector-ROIC monolithic structure, for example darkcurrent density characteristic. Moreover, the grain boundary passivationwith hydrogen atoms in a controlled manner using gas plasma pulsing atlow temperature does not negatively impact the underlyingmicroelectronic circuitry of the ROIC portion of the polycrystalline IRdetector-ROIC monolithic structure.

In accordance with some embodiments herein, the above-describedpolycrystalline IR detector structure 200 has one or both of a darkcurrent density characteristic and a diode spectral responsesubstantially comparable to single-crystalline Group III-V compoundsemiconductor IR detectors. For example, for a given temperature (e.g.,in degrees Kelvin), single-crystalline Group III-V compoundsemiconductor IR detectors may achieve a dark current density that isinfinitesimally small at a reverse bias voltage of about 50.0 millivolts(mV) (e.g., dark current density within a range of from about 10⁻² toabout 10⁻¹ Amps per square centimeter (A/cm²) at an operatingtemperature of 230K). The polycrystalline Group III-V compoundsemiconductor IR detector structure in accordance with the variousembodiments of the present invention described herein has a dark currentdensity characteristic that may be substantially comparable to that ofits counterpart single-crystalline Group III-V compound semiconductor IRdetector. Performance metrics for an example polycrystalline IR detectorstructure that was fabricated in accordance to an embodiment of themethod 100 described herein are further described below with respect tothe Example.

Example

A polycrystalline InAs barrier detector structure was fabricated on anamorphous template. The amorphous template used was a Czochralski (CZ)silicon wafer that was thermally oxidized to form a SiO₂ surface layer(i.e., amorphous surface). The amorphous template used was intended tosimulate a surface of an ROIC wafer. After a hydrogen gas (H₂)desorption step at 400° C. to remove contamination from the SiO₂ wafersurface, InAs compound semiconductor material was deposited directlyonto the oxidized silicon wafer. The polycrystalline InAs material wasdoped during deposition with silicon (Si) as an n-type dopant at avarying concentration level (gradient) to form a contact layer of higherdopant concentration and an absorber layer with a relatively lowerdopant concentration.

After a pause of 40 seconds to transition from In and As fluxes to Aland Sb fluxes, AlSb compound semiconductor material was then depositedon the polycrystalline InAs material as a barrier layer. Thepolycrystalline AlSb material layer was doped with beryllium (Be) as ap-type dopant during deposition. After another pause of 400 seconds topermit changes in the Be dopant atom flux and In and As fluxes, InAs wasdeposited on the polycrystalline AlSb layer and doped during depositionwith the p-type dopant at a higher dopant concentration than the AlSblayer. A p-n type detector semiconductor junction was formed in thefabricated polycrystalline detector structure.

The InAs and AlSb compound semiconductor materials were deposited anddoped using molecular beam epitaxy at a deposition temperature of 325°C. Table 1 summarizes some parameters of the deposition process used.The thickness and total depth values in Table 1 were nominal valuesspecified in Angstroms (Å).

FIG. 4 illustrates a graph of an X-ray diffraction spectrum of thepolycrystalline InAs barrier detector structure formed using theabove-described parameters, collected on a Phillips X'pertDiffractometer (PANalytical, Almelo, Netherlands). The various numbersin parenthesis in FIG. 4 are Miller indices of the crystal planes of thepolycrystalline material responsible for the various peaks in the X-rayspectrum.

TABLE 1 Deposition parameters of fabricated polycrystalline InAs barrierdetector structure Total Layer Material Thickness (Å) Depth (Å) Doping(cm³) p⁺ Contact InAs  1000  1000 Be = 5 × 10¹⁷ PAUSE Barrier AlSb  1200 2200 Be = 2 × 10¹⁶ PAUSE n⁻ Absorber InAs 15000 17200 Si = l × 10¹⁶Grade to n⁻ InAs   500 17700 Si = 5 × 10¹⁷ to l × 10¹⁶ n⁺ Contact InAs 1000 18700 Si = 5 × 10¹⁷ PAUSE: H₂ Desorb Substrate CZ Si: Oxidized

To evaluate the dark current density and diode spectral response of thefabricated polycrystalline InAs barrier detector structure, thefabricated detector structure wafer was then divided into individualInAs barrier detector chips ranging in size from about 100 microns (μm)to about 400 μm. For evaluation only, a wet chemical etch was used todelineate the individual detector diodes. The dark current density wasevaluated over a bias voltage range of −1.0V to 0.2V using an AgilentB1500 Semiconductor Device Analyzer (Keysight Technologies, CA).

FIG. 5A illustrates a graph of dark current density versus reverse biasvoltage for the fabricated InAs barrier detector example, at atemperature of 240 K. From the graph in FIG. 5A, the dark currentdensity measured at a reverse bias of −0.2 V for the fabricatedpolycrystalline InAs barrier detector example was about 3×10⁻² Å/cm².The reverse bias of −0.2 V represents an operational reverse biasvoltage that can typically range from about −50 mV to −200 mV. Thevalues measured for the fabricated InAs barrier detector example areconsistent with performance metrics of comparable single-crystallineInAs detectors. FIG. 6 illustrates a graph of dark current densityversus reverse bias voltage for a single-crystalline detector as acomparison. The dark current density of single-crystalline detector isabout 4×10⁻² Å/cm² at a reverse bias of −200 mV in FIG. 6.

The diode spectral response of the fabricated InAs barrier detectorexample was measured in a wavelength range of 2.0 microns to 5.0 micronsat a temperature of 85 K (T=85K) using a Thermo-Nicolet Nexus 670 FTIRspectrometer (Thermo Fisher Scientific, Waltham, Mass.). FIG. 5Billustrates a graph of diode spectral response per photon versuswavelength of the fabricated polycrystalline InAs barrier detectorexample at the temperature of 85 K. From the graph in FIG. 5B, thespectral response (diode response (per photon)) of the fabricatedpolycrystalline InAs barrier detector example indicates that the devicehas a cutoff wavelength of 3.03 μm as determined by the semiconductingbandgap of the polycrystalline InAs. As a comparison, a typicalsingle-crystalline InAs detector may have a cut-off wavelength within arange of 3 μm and 3.5 μm, depending on the temperature (e.g., 77 K to195 K).

The performance metrics achieved for the InAs barrier detector exampleare representative of metrics achievable by the polycrystalline GroupIII-V compound semiconductor IR detector structure that is fabricatedand monolithically integrated according to the principles of the presentinvention. As such, the principles of the present invention, asdescribed herein, enable a polycrystalline Group III-V compoundsemiconductor IR detector to be utilized as FPA detectors directly onSi-based ROIC wafers in wafer-level fabrication. Concomitantly, theconventional time-consuming and costly steps that include indium-bumpingindividual single-crystalline detector die or chips and individual ROICdie in a die-level hybridization process to form an FPA may be avoided.

Thus, there have been described examples of a polycrystalline IRdetector a method of fabricating polycrystalline IR detector structuresand a method of monolithic integration of polycrystalline IR detectorstructures with FPAs using wafer-level fabrication, both methods at lowtemperature on amorphous templates. It should be understood that theabove-described embodiments and examples are merely illustrative of someof the many specific examples and embodiments that represent theprinciples consistent with the principles described herein. Clearly,those skilled in the art can readily devise numerous other arrangementswithout departing from the scope consistent with the principlesdescribed herein as defined by the following claims.

What is claimed is:
 1. A method of fabricating a polycrystallineinfrared (IR) detector structure, the method comprising: providing anamorphous template; and depositing a Group III-V compound semiconductormaterial directly on the amorphous template at a low depositiontemperature that is within a range of about 300° C. to about 400° C.,wherein depositing a Group III-V compound semiconductor materialcomprises doping the Group III-V compound semiconductor material with adopant profile to form the polycrystalline IR detector structure havinga detector semiconductor junction.
 2. The method of fabricating apolycrystalline IR detector structure of claim 1, wherein thetemperature range of depositing the Group III-V compound semiconductormaterial is about 300° C. to about 375° C., the Group III-V compoundsemiconductor material comprising one or more of indium, aluminum,gallium, arsenic and antimony.
 3. The method of fabricating apolycrystalline IR detector structure of claim 1, wherein thetemperature range of depositing the Group III-V compound semiconductormaterial is about 300° C. to about 350° C., and wherein the amorphoustemplate is a semiconductor substrate having amorphous surface.
 4. Themethod of fabricating a polycrystalline IR detector structure of claim1, wherein the temperature range of depositing the Group III-V compoundsemiconductor material is about 300° C. to about 325° C., and whereindepositing a Group III-V compound semiconductor material with a dopantprofile comprises: depositing a first Group III-V compound semiconductormaterial and a first dopant with a gradient of different dopant levels;depositing a second Group III-V compound semiconductor material and asecond dopant with a second dopant level on the doped first Group III-Vcompound semiconductor material; and depositing the first Group III-Vcompound semiconductor material and the second dopant with a firstdopant level on the doped second Group III-V compound semiconductormaterial to form the dopant profile of the detector semiconductorjunction.
 5. The method of fabricating a polycrystalline IR detectorstructure of claim 1, wherein the temperature range of depositing theGroup III-V compound semiconductor is about 300° C. to about 350° C.,and wherein the amorphous template is an amorphous surface of a readoutintegrated circuit (ROIC) wafer, the deposition directly on theamorphous surface monolithically integrates the polycrystalline IRdetector structure with the ROIC wafer to form pixels of a focal planearray.
 6. The method of fabricating a polycrystalline IR detectorstructure of claim 1, wherein the polycrystalline IR detector structurehas one or both of a dark current characteristic and a diode spectralresponse substantially comparable to single-crystalline Group III-Vcompound semiconductor IR detectors.
 7. The method of fabricating apolycrystalline IR detector structure of claim 1, wherein the depositionof the Group III-V compound semiconductor material is performed usingone of molecular beam epitaxy and metal organic chemical vapordeposition.
 8. The method of fabricating a polycrystalline IR detectorstructure of claim 1, wherein depositing a Group III-V compoundsemiconductor material comprises: depositing a first contact layer of afirst Group III-V compound semiconducting material on the amorphoustemplate, the first contact layer being polycrystalline with a firstdoping level; depositing an absorber layer of a second Group III-Vcompound semiconducting material on the deposited first contact layer,the absorber layer being polycrystalline with a second doping level;depositing a barrier layer of a third Group III-V compoundsemiconducting material on the deposited absorber layer, the barrierlayer being polycrystalline with a third doping level; and depositing asecond contact layer of a fourth Group III-V compound semiconductingmaterial on the barrier layer, the second contact layer beingpolycrystalline with a fourth doping level, wherein the doping levelsform the dopant profile of the detector semiconductor junction of thepolycrystalline IR detector structure.
 9. The method of fabricating apolycrystalline IR detector structure of claim 8, wherein depositing thefirst contact layer comprises: depositing indium arsenide (InAs) havingan n⁺-type or p⁺-type dopant and the first doping level, and grading thefirst doping level from the n⁺-type or p⁺-type doping level to acorresponding n⁻-type or p⁻-type doping level at a surface of the firstcontact layer; wherein depositing the absorber layer comprisesdepositing InAs with the corresponding n⁻-type or p⁻-type dopant and thesecond doping level on the first contact layer surface; whereindepositing the barrier layer comprises depositing aluminum antimonide(AlSb) on a surface of the absorber layer, the AlSb barrier layer havingthe third doping level and either a same or an opposite dopant type tothe n⁻-type or p⁻-type dopant of the absorber layer; and whereindepositing the second contact layer comprises depositing InAs havingeither a same or an opposite dopant type to the n⁺-type or p⁺-typedopant of the first contact layer, the fourth doping level of the secondcontact layer being substantially similar to the first doping level ofthe first contact layer, the polycrystalline IR detector structure beinga InAsSb mid-wave IR detector.
 10. The method of fabricating apolycrystalline IR detector structure of claim 1, further comprisingpassivating grain boundaries of the polycrystalline IR detector withcontrolled pulses of a gas plasma comprising a carrier gas and hydrogengas at a temperature maintained within a range of about 100° C. to lessthan 200° C. for a period of time to incorporate hydrogen atoms into thegrain boundaries.
 11. A method of monolithic integration of an infrared(IR) detector structure in a focal plane array, the method comprising:providing a readout integrated circuit (ROIC) wafer with an amorphoussurface; and depositing Group III-V compound semiconductor materialsdirectly on the amorphous surface of the ROIC wafer at a low temperaturewithin a range of about 300° C. to less than 400° C. to form apolycrystalline IR detector structure having a semiconductor junction onthe ROIC wafer, wherein the polycrystalline IR detector structuredirectly on the ROIC wafer forms a monolithically integrated structureto provide an IR focal plane array.
 12. The method of monolithicintegration of claim 11, wherein the Group III-V compound semiconductormaterials of the polycrystalline IR detector structure comprises two ormore of indium, aluminum, gallium, arsenic and antimony.
 13. The methodof monolithic integration of claim 11, wherein the Group III-V compoundsemiconductor materials are deposited on the amorphous surface of theROIC wafer at a temperature within the range of about 300° C. to about375° C.
 14. The method of monolithic integration of claim 11, whereinthe polycrystalline IR detector structure has one or both of a darkcurrent characteristic and a diode spectral response substantiallycomparable to a single-crystalline Group III-V compound semiconductor IRdetector.
 15. The method of monolithic integration of claim 11, furthercomprising passivating grain boundaries of the formed polycrystalline IRdetector structure in a controlled manner with hydrogen atoms, whereinpassivating grain boundaries comprises exposing the monolithicallyintegrated structure to controlled pulses of a gas plasma comprising acarrier gas and hydrogen gas at a temperature maintained within a rangeof about 100° C. to less than 200° C. for a period of time.